| 摘要 |
<p>A SEMICONDUCTOR CHIP IS DEFINED TO INCLUDE A LOGIC BLOCK AREA HAVING A FIRST CHIP LEVEL IN WHICH LAYOUT FEATURES ARE PLACED ACCORDING TO A FIRST VIRTUAL GRATE, AND A SECOND CHIP LEVEL IN WHICH LAYOUT FEATURES ARE PLACED ACCORDING TO A SECOND VIRTUAL GRATE. A RATIONAL SPATIAL RELATIONSHIP EXISTS BETWEEN THE FIRST AND SECOND VIRTUAL GRATES. A NUMBER OF CELLS ARE PLACED WITHIN THE LOGIC BLOCK AREA. EACH OF THE NUMBER OF CELLS IS DEFINED ACCORDING TO AN APPROPRIATE ONE OF A NUMBER OF CELL PHASES. THE APPROPRIATE ONE OF THE NUMBER OF CELL PHASES CAUSES LAYOUT FEATURES IN THE FIRST AND SECOND CHIP LEVELS OF A GIVEN PLACED CELL TO BE ALIGNED WITH THE FIRST AND SECOND VIRTUAL GRATES AS POSITIONED WITHIN THE GIVEN PLACED CELL.</p> |
