Synchronizer circuits with failure-condition detection and correction

摘要

An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.

主权项

1. A synchronizer circuit, comprising:
a first resettable flip-flop comprising a first data input to receive an input signal, a first reset input to receive a reset signal, and a first data output to provide a first output signal, wherein the first resettable flip-flop is to produce transitions of the first output signal from a first logic state to a second logic state in response to corresponding transitions of the input signal and is to produce transitions in the first output signal from the second logic state to the first logic state in response to assertion of the reset signal; a detector circuit to assert a warning signal in response to transitions of the input signal from the second logic state to the first logic state; and a logic gate to forward the first output signal when the warning signal is de-asserted and to provide a signal in the first logic state in response to assertion of the warning signal.