| 摘要 |
PROBLEM TO BE SOLVED: To provide a low-power, current-mode-logicless transmitter architecture.SOLUTION: The exemplary embodiments of the present invention relate to a low-power current-mode-logicless (CML-less) transmitter architecture. A transmitter comprises: a main multiplexer configured to generate a main data signal by multiplexing a retimed parallel main data signal, from a retimer, for a time margin between a parallel input data signal and a multi-phase clock signal from a clock distributor; a secondary multiplexer configured to generate a post-data signal by multiplexing a retimed parallel post-data signal from the retimer; and a plurality of output drivers configured to generate serial data signals by adding the main data signal and the post-data signal. |
