NODE PROCESSOR FOR USE IN PARITY CHECK DECODER

摘要

PROBLEM TO BE SOLVED: To provide techniques for implementing message passing decoders, e.g., LDPC decoders.SOLUTION: To facilitate hardware implementation, messages are quantized to integer multiples of 1/2 ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented with the use of an accumulator module 1302, a subtracter module 1304 and a delay pipeline 1306. Delayed input messages from the delay pipeline 1306 are subtracted from an accumulated message sum 1316 to generate output messages 1321.