IMAGE PROCESSOR

摘要

The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

主权项

1. An image processor that derives a predetermined parameter to be included in a Network Abstraction Layer (NAL) unit packet in generating a NAL unit packet in compression coding of a moving image, the image processor comprising:
a ⅓ multiplier circuit configured to approximately multiply an input value by ⅓, the ⅓ multiplier circuit including a loop operation circuit configured to repeatedly perform a predetermined operation by loops; and a setting circuit configured to set a required number of loops in the loop operation circuit, the loop operation circuit having a register configured to receive an input of an input value; a bit shift circuit configured to perform bit shift by 2 bits to the right on a value output from the register; and an adder circuit configured to add an input value and a value output from the bit shift circuit, and input an added value to the register.