| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock output circuit 1 that outputs a clock having a stable frequency while reducing current consumption.SOLUTION: The clock output circuit includes: NOT gates 21A, 22A for logically negating an oscillation signal output from an oscillation circuit 10; a NOT gate 23 for logically negating an output signal of the NOT gate 21A; and an RS flip-flop circuit 24 for receiving output signals of the NOT gates 22A, 23 as input signals. A first threshold Th1 of the NOT gate 21A is greater than a second threshold Th2 of the NOT gate 22A, the first threshold Th1 increases with increasing frequency of the oscillation signal, and the second threshold Th2 decreases with increasing frequency of the oscillation signal. Before the oscillation of an oscillator 11 of the oscillation circuit 10 stabilizes, the RS flip-flop circuit 24 waits to output a source clock, and when the frequency decreases, the RS flip-flop circuit 24 outputs the source clock. |
