Pseudo self aligned radhard MOSFET and process of manufacture

摘要

A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.

主权项

1. A method of fabricating a semiconductor device on a substrate of a first conductivity type, the method comprising:
forming a sacrificial oxide layer on the substrate; forming a sacrificial masking layer on the sacrificial oxide layer; forming a body and source implant pattern in the sacrificial masking layer, exposing a portion of the surface of the sacrificial oxide layer; implanting and diffusing a dopant in the substrate through the body and source implant pattern to form a body region of the second conductivity type; removing the exposed sacrificial oxide within a portion of the body and source implant pattern, exposing a first portion of the top surface of the substrate bounded by sidewalls of the sacrificial masking layer; implanting a dopant in the substrate through the body and source implant pattern to form a source region of the first conductivity type; forming spacer walls on the sidewalls of the sacrificial masking layer to define a UIS implant pattern; implanting a dopant in the substrate through the UIS implant pattern to form a UIS region of the second conductivity type; diffusing the source region to form a channel region with a body region boundary and a source region boundary that are tightly aligned; removing the spacer walls, remnants of the sacrificial masking layer, and remnants of the sacrificial oxide layer to expose the top surface of the substrate; forming a late gate oxide layer on the exposed top surface of the substrate; forming a polysilicon layer on the late gate oxide layer; and removing a portion of the polysilicon layer above the source region in the substrate to expose a first surface of the late gate oxide layer overlaying the source region and to retain a portion of the polysilicon layer on the gate oxide layer overlapping the channel region.