Tapered via and MIM capacitor

摘要

A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

主权项

1. A method comprising:
selecting an insulating substrate having an upper surface and having a first wire in said insulating substrate; forming a first insulating layer over said upper surface of said insulating substrate and over said first wire; forming a first tapered opening in said first insulating layer over said first wire exposing said upper surface of said first wire; forming a bottom electrode of a capacitor on said first insulating layer; forming a first conductor over said upper surface of said first wire, said first tapered opening and said first insulating layer to said bottom electrode; forming a second insulating layer over said bottom electrode; and forming a top electrode of said capacitor on said second insulating layer positioned over said bottom electrode, said top electrode having a periphery interior of a periphery of said bottom electrode.