ANALYZING TIMING REQUIREMENTS OF A HIERARCHICAL INTEGRATED CIRCUIT DESIGN

摘要

Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete.

主权项

1. A computer-implemented method for analyzing timing requirements of a hierarchical integrated circuit design, the method comprising:
marking each logic gate in a child unit of the hierarchical integrated circuit design that is visible in an abstract model of the child unit of the hierarchical integrated circuit design; and preserving each marked logic gate in the child unit during modification of the child unit.