THREAD-SUSPENDING EXECUTION BARRIER

摘要

An energy-efficient execution barrier for parallel processing is provided. The execution barrier associates a thread-execution bit with each hardware-supported thread. The energy-efficient execution barrier utilizes a per-processor or per-chip bit vector register, having, for example, one bit per possible thread. A bit enables or disables the execution of its corresponding thread. A process starts by forking threads and enabling them in the bit vector register. When a thread arrives at the barrier/rendezvous, the thread disables its own bit and therefore suspends thread execution. When a distinguished thread arrives at the barrier, it waits (e.g., spinlocks) until all the threads needed for the rendezvous are disabled. The distinguished thread (or an automatic thread re-enable mechanism) then atomically sets all threads bits in the bit vector register to enabled, and the threads perform any appropriate sync operations and continue.

主权项

1. A processing apparatus comprising:
a processing structure configured to execute program code using a plurality of threads; a bit register including a plurality of bits, wherein during operation each thread being executed by the processing structure corresponds to a bit of the plurality of bits, wherein each of the plurality of threads can change its corresponding bit from a first state to a second state, wherein the execution of the program code of each of the plurality of threads is suspended when its corresponding bit is in the second state; and a thread re-enablement entity for changing the corresponding bits for the plurality of bits from the second state to the first state to re-enable execution of the program code of the plurality of threads.