POWER MANAGEMENT FOR A MEMORY DEVICE

摘要

An improved method and apparatus for performing power management in a memory device is disclosed.

主权项

1. A power management circuit for use in a memory device, comprising:
a system device clock for generating a clock signal; a timing circuit for identifying a time interval; a first circuit for receiving the clock signal and counting pulses of the clock signal within the time interval; a second circuit for changing the bias voltage of a sense amplifier in response to the output of the counter circuit.