INSTRUCTION BOUNDARY PREDICTION FOR VARIABLE LENGTH INSTRUCTION SET

摘要

A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

主权项

1. A processor, comprising:
an instruction fetch unit to provide an instruction address; an instruction cache to produce an instruction tag and instruction cache content corresponding to the instruction address; a boundary byte predictor to receive the instruction tag and generate a prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes; and an instruction decoder including boundary byte logic to determine an instruction boundary in the instruction cache content, wherein the boundary byte logic forms an initial prediction of a boundary byte based on the prediction vector.