发明名称 SYSTEMS AND METHODS FOR IMPLEMENTING TRANSACTIONAL MEMORY
摘要 Systems and methods for implementing transactional memory access. An example method may comprise initiating a memory access transaction; executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to the first memory location or the second memory location, aborting the memory access transaction; and completing, irrespectively of the state of the third memory location and the fourth memory location, the memory access transaction responsive to failing to detect a transaction aborting condition.
申请公布号 US2014281236(A1) 申请公布日期 2014.09.18
申请号 US201313803658 申请日期 2013.03.14
申请人 Rash William C.;Hahn Scott D.;Toll Bret L.;Hinton Glenn J. 发明人 Rash William C.;Hahn Scott D.;Toll Bret L.;Hinton Glenn J.
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项 1. A method, comprising: initiating, by a processor, a memory access transaction; executing at least one of: a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing at least one of: a non-transactional read operation with respect to a third memory location, or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to at least one of the first memory location or the second memory location, aborting the memory access transaction; and responsive to failing to detect a transaction aborting condition and irrespectively of a state of the third memory location and a state of the fourth memory location, completing the memory access transaction.
地址 Saratoga CA US