SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

摘要

A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.

主权项

1. A method of semiconductor fabrication, comprising:
forming a plurality of first transistors having a first operating voltage, the plurality of first transistors comprising a plurality of first gate structures over a first transistor region of a substrate, a plurality of low voltage shallow wells adjacent the plurality of first gate structures and a plurality of low voltage pocket implants adjacent the plurality of first gate structures; and forming a plurality of second transistors having a second operating voltage adjacent the plurality of first transistors, the forming a plurality of second transistors comprising:
forming a first high voltage photoresist over the plurality of first gate structures, over the first transistor region and over a plurality of second gate structures, the plurality of second gate structures over a second transistor region of the substrate, such that a plurality of high voltage implant areas of the substrate adjacent the plurality of second gate structures and a plurality of second gate top portions of the plurality of second gate structures are exposed;performing a high voltage LDD implant at a first high energy to implant a first high voltage dopant into the plurality of high voltage implant areas to form a plurality of high voltage shallow wells adjacent the plurality of second gate structures; andperforming a high voltage pocket implant at a second high energy to implant a second high voltage dopant into the plurality of high voltage implant areas to form a plurality of high voltage pocket implants adjacent the plurality of second gate structures.