| 发明名称 |
Stress Tuning for Reducing Wafer Warpage |
| 摘要 |
An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer. |
| 申请公布号 |
US2014264931(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313946728 |
申请日期 |
2013.07.19 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wang Yung-Yao;Chiou Ying-Han;Wang Ling-Sung |
| 分类号 |
H01L23/532;H01L21/768 |
主分类号 |
H01L23/532 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit structure comprising:
a substrate; a plurality of low-k dielectric layers over the substrate; a first dielectric layer over the plurality of low-k dielectric layers; a metal line in the first dielectric layer; a stress tuning dielectric layer over the first dielectric layer, wherein the stress tuning dielectric layer comprises:
a first opening, wherein the metal line extends into the first opening; anda second opening with a bottom substantially level with a top surface of the first dielectric layer; and a second dielectric layer over the first dielectric layer. |
| 地址 |
Hsin-Chu TW |
