Global Synchronous Clock

摘要

Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

主权项

1. A computer comprising:
a first printed circuit board comprising:
a memory;an integrated circuit processor:
coupled to the memory;comprising a processor clock signal input port configured to receive a first processor clock signal; andconfigured to execute instructions, fetched from the memory, at a speed determined by the first processor clock signal;a first network port configured to be connectable to a first synchronous communication network;a first physical layer interface coupled to the first network port and configured to recover a first recovered clock signal from a signal received via the first synchronous communication network; anda clock signal distribution circuit configured to:
receive the first recovered clock signal;generate the first processor clock signal therefrom; anddeliver the first processor clock signal to the processor clock signal input port; whereby the first processor clock signal delivered to the clock signal input port of the integrated circuit processor is based on a signal generated external to the first printed circuit board.