发明名称 Method for reducing a minimum line width in a spacer-defined double patterning process
摘要 The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.
申请公布号 US8835322(B2) 申请公布日期 2014.09.16
申请号 US201113339559 申请日期 2011.12.29
申请人 Shanghai Huali Microelectronics Corporation 发明人 Yu Liujiang
分类号 H01L21/311;H01L21/033 主分类号 H01L21/311
代理机构 McDonnell Boehnen Hulbert & Berghoff LLP 代理人 McDonnell Boehnen Hulbert & Berghoff LLP
主权项 1. A method for reducing a minimum line width in a spacer-defined double patterning process, comprising the following steps of: step S1: providing a silicon substrate, and depositing in sequence a layer of lower layer medium, an interlayer dielectric layer and a sacrificial hard mask layer on the silicon substrate; step S2: coating a layer of photoresist on the sacrificial hard mask layer, and performing a lithography process; step S3: etching the sacrificial hard mask layer by using the photoresist as a mask to form retention structures of the sacrificial hard mask layer, and removing the photoresist; step S4: depositing a layer of silicon nitride film on the interlayer dielectric layer and the retention structures of the sacrificial hard mask layer, etching the silicon nitride film with a dry etching process to form silicon nitride spacers on both sides of the retention structures of the sacrificial hard mask layer, and then removing the retention structures of the sacrificial hard mask layer; step S5: depositing a layer of silicon dioxide film on the interlayer dielectric layer and the silicon nitride spacers; step S6: performing a planarization process on the silicon dioxide film such that the height of the silicon dioxide film around the silicon nitride spacer corresponds to the height of the silicon nitride spacer; step S7: removing the silicon nitride spacers to form trenches at the positions where the silicon nitride spacers are removed in the silicon dioxide film; and step S8: etching the interlayer dielectric layer by using the silicon dioxide film as a mask and by means of the trenches in the silicon dioxide film, to form desired trenches in the interlayer dielectric layer, and then removing the silicon dioxide film, wherein the trenches are formed in the silicon dioxide film in step S7 only at positions where the silicon nitride spacers are removed, and wherein the trenches are formed in the interlayer dielectric layer in step S8 only where the trenches are formed in the silicon dioxide film.
地址 Pudong, Shanghai CN