Tunnel-effect transistor

摘要

The transistor (100) has source and drain extension regions (102, 103) on either side of a channel (101), where source and drain conductive regions (104, 105) are in contact with the extension regions. A gate structure (106) includes a gate dielectric layer (108) in contact with the channel. A gate area (107) is arranged such that the gate dielectric layer is arranged between the gate area and the channel. A doped area (120) is inserted between the channel and the drain extension region, to form a barrier for preventing charge carriers from escaping from the drain extension region.