发明名称 Netlisting analog/mixed-signal schematics to VAMS
摘要 A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.
申请公布号 US8832612(B1) 申请公布日期 2014.09.09
申请号 US201314073634 申请日期 2013.11.06
申请人 Cadence Design Systems, Inc. 发明人 O'Riordan Donald J.;Bhattacharya Prabal Kanti;O'Leary Timothy Martin
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Kenyon & Kenyon LLP 代理人 Kenyon & Kenyon LLP
主权项 1. A method to convert an analog mixed-signal schematic design in non-transitory storage to a digital netlist in non-transitory storage, the method comprising: converting digital blocks within the schematic design to corresponding digital netlist modules in non-transitory storage; converting analog blocks within the schematic design to corresponding analog netlist modules in non-transitory storage; determining whether respective analog netlist modules correspond to analog blocks within the schematic design that are contained within a view within the schematic design that also contains a respective digital block; in response to determining that a respective analog netlist module corresponds to a respective analog block within the schematic design that is contained within a respective view within the schematic design that also contains a respective digital block, determining whether the respective analog block shares a respective component within the schematic design with the respective digital block; in response to determining that the respective analog block shares a respective component within the schematic design with the respective digital block, selecting an identifier for the component within the respective analog netlist module that matches an identifier for the same component within a respective digital netlist module that corresponds to the respective digital block within the view; converting the analog netlist modules to corresponding digital netlist modules in non-transitory storage; and producing a mapping file in non-transitory storage that includes a mapping between the identifiers used in one or more digital netlist files and identifiers used to identify corresponding components in the schematic design.
地址 San Jose CA US