Wafer level chip scale package and method of fabricating wafer level chip scale package

摘要

A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.

主权项

1. A method of fabricating a wafer level chip scale package comprising:
printing a first dielectric layer on a carrier; forming a main through hole in the first dielectric layer to expose the carrier; forming an adhesive layer on a surface of the carrier exposed through the main through hole of the first dielectric layer; attaching a semiconductor die to the adhesive layer; forming a redistribution layer coupled to the semiconductor die and the first dielectric layer; printing a second dielectric layer on the first dielectric layer and the redistribution layer; forming an opening in the second dielectric layer to expose the redistribution layer; forming an under bump metal coupled to the redistribution layer through the opening; and coupling a solder ball to the under bump metal.