Enhanced FinFET process overlay mark

摘要

An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

主权项

1. A method comprising:
receiving a substrate having an overlay region; forming one or more dielectric layers on the substrate; forming a hard mask layer on the one or more dielectric layers; patterning the hard mask layer to form a hard mask layer feature, the hard mask layer feature configured to define an overlay mark fin disposed within the overlay region; forming a spacer on the patterned hard mask layer, the spacer further defining the overlay mark fin; cutting the overlay mark fin to form a fin line-end defining a reference location for mask overlay metrology; etching the one or more dielectric layers using the spacer, the etching of the dielectric layers further defining the overlay mark fin; and etching the substrate using the etched one or more dielectric layers, the etching of the substrate further defining the overlay mark fin.