CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING

摘要

A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

主权项

1. A method for equalizing time delays in a pulse width modulation (PWM) system, said method comprising the steps of:
determining a maximum propagation delay of a one of a plurality of PWM signals; determining propagation delays of other ones of the plurality of PWM signals; subtracting each of the propagation delays of the other ones of the plurality of PWM signals from the maximum propagation delay; and adding a time delay to each of the other ones of the plurality of PWM signals that is substantially equal to a difference between the maximum propagation delay and the propagation delay of the respective other one of the plurality of PWM signals.