发明名称 Method for fabricating a semiconductor device having a saddle fin transistor
摘要 A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.
申请公布号 US8815689(B2) 申请公布日期 2014.08.26
申请号 US201313875561 申请日期 2013.05.02
申请人 SK hynix Inc. 发明人 Lee Jin Yul;Kim Dong Seok
分类号 H01L21/336;H01L29/66;H01L27/108;H01L29/78 主分类号 H01L21/336
代理机构 Marshall, Gerstein & Borun LLP 代理人 Marshall, Gerstein & Borun LLP
主权项 1. A method for fabricating a semiconductor device having a saddle fin transistor, comprising: forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench, the isolation layer defining an active region of the semiconductor substrate; etching the active region of the semiconductor substrate by a selected depth to form a recessed active region; etching the isolation layer adjacent to the recessed active region by a selected depth to form a recessed isolation region, whereby the recessed active region protrudes from the recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region; processing the gate metal layer to form a gate of a cell transistor buried under a surface of the semiconductor substrate in the recessed active region; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.
地址 Icheon-Si KR