发明名称 |
METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING |
摘要 |
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. |
申请公布号 |
US2014231871(A1) |
申请公布日期 |
2014.08.21 |
申请号 |
US201414263708 |
申请日期 |
2014.04.28 |
申请人 |
INTEL CORPORATION |
发明人 |
Goel Niti;Pillarisetty Ravi;Mukherjee Niloy;Chau Robert S.;Rachmady Willy;Metz Matthew V.;Le Van H.;Kavalieros Jack T.;Radosavljevic Marko;Chu-Kung Benjamin;Dewey Gilbert;Sung Seung Hoon |
分类号 |
H01L29/78;H01L27/092;H01L21/8238 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a semiconductor device comprising a channel material having a first lattice structure on a well of a well material having a matched lattice structure, the well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, wherein the well comprises dimensions of a height greater than each of a width and a length. |
地址 |
Santa Clara CA US |