Nanowire FET and FinFET hybrid technology

摘要

Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

主权项

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:
a wafer having a buried oxide (BOX) and an active layer on the BOX, wherein the active layer is configured to have at least one first region with a thickness t1 and at least one second region with a thickness t2, and wherein t2 is less than t1; a nanowire field-effect transistor (FET) on the BOX formed in the second region of the active layer comprising:
nanowires and pads patterned in the second region of the active layer, wherein the pads are attached at opposite ends of the nanowires in a ladder-like configuration, and wherein the nanowires are suspended over the BOX;a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack serve as a channel region of the nanowire FET;an epitaxial material on portions of the nanowires and pads that serve as source and drain regions of the nanowire FET; a finFET on the BOX formed in the first region of the active layer comprising:
a plurality of fins patterned in the first region of the active layer, wherein a height of the fins patterned in the first region of the active layer is greater than a thickness of the nanowires and pads patterned in the second region of the active layer based on the first region of the active layer being thicker than the second region of the active layer;a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack serve as a channel region of the finFET; andan epitaxial material on portions of the fins that serve as source and drain regions of the finFET.