发明名称 Phase locked loop circuit with reduced jitter
摘要 A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.
申请公布号 US8803572(B2) 申请公布日期 2014.08.12
申请号 US201213547742 申请日期 2012.07.12
申请人 STMicroelectronics International N.V. 发明人 Kumar Anand;Dhadda Pradeep
分类号 H03L7/06 主分类号 H03L7/06
代理机构 Graybeal Jackson LLP 代理人 Graybeal Jackson LLP
主权项 1. A circuit, comprising: a filter configured to produce a first filtered signal and a second filtered signal; and an oscillator coupled to the filter and configured to modify the first filtered signal in a manner that is different from modifying the second filtered signal, the difference including a scaling factor.
地址 Amsterdam NL