SYSTEM AND METHOD TO DESIGN AND TEST A YIELD SENSITIVE CIRCUIT

摘要

A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.

主权项

1. A method of designing a semiconductor device within a circuit design application of a computer, comprising:
determining a design of a semiconductor device to be fabricated; identifying at least a portion of the design of the semiconductor device to be a yield sensitive circuit by comparing said at least the portion of the design of the semiconductor device to previously known yield sensitive circuits; and inserting the yield sensitive circuit, identified by comparing said at least the portion of the design of the semiconductor device to previously known yield sensitive circuits, between a first pair of flip flops to form a scan chain with the yield sensitive circuit within the design of the semiconductor device, the yield sensitive circuit being and connected to the first pair of flip flops.