Delay locked loop circuit and integrated circuit including the same

摘要

A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

主权项

1. A delay locked loop (DLL) circuit comprising:
a timing pulse generating unit configured to generate a plurality of timing pulses pulsed sequentially for delay shifting update periods in response to a source clock, wherein the number of the generated timing pulses changes according to a change in a frequency of the source clock during an operation of the DLL circuit; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay duplication modeling unit configured to delay an output clock of the clock delay unit by an actual delay of the internal clock path, and to output the delayed clock as the feedback clock.