Updating programmable logic devices in a multi-node system configured for symmetric multiprocessing

摘要

Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

主权项

1. A method of updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each PLD configured according to configuration instructions installed within each PLD,
the SMP computer comprising a plurality of compute nodes including a primary compute node and one or more secondary compute nodes, the compute nodes sharing a same memory address space, each compute node further comprising a PLD coupled for data communications to at least one computer processor through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, each bus adapter defaulting, upon a stand-alone boot, to a same set of one or more I/O memory addresses, the method comprising: configuring the primary compute node with an update of the configuration instructions for the PLDs; and for each PLD of each secondary compute node, transmitting, by the primary compute node, the update to the PLD using a set of one or more I/O addresses corresponding to a particular bus adapter associated with a particular PLD.