Weak bit detection in a memory through variable development time

摘要

Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.

主权项

1. An apparatus, comprising:
a plurality of columns, wherein each of the plurality of columns includes a respective plurality of data storage cells and a respective pre-charge circuit;
wherein each given one of the plurality of data storage cells is configured such that in response to the assertion of a respective one of a plurality of row selection signals, the given data storage cell generates a corresponding column output; andwherein the pre-charge circuit is configured to selectively provide a first pre-charge current or a second pre-charge current dependent upon a pre-charge control signal; a column multiplexer coupled to receive input data from column outputs of the plurality of columns, wherein the column multiplexer is configured to controllably select input data from the plurality of columns dependent upon a column selection signal to generate a column multiplexer output; a sense amplifier configured to amplify the column multiplexer output by a gain level of the sense amplifier in response to assertion of an amplifier enable signal; a selection circuit configured to generate the plurality of row selection signals and the plurality of column selection signals dependent upon an input address and in response to the assertion of a selection enable signal; and a timing and control unit configured to generate the pre-charge control signal and the selection enable signal; wherein the timing and control unit is further configured to selectively generate the amplifier enable signal either a first time period or a second time period after generation of the selection enable signal, dependent upon a timing selection signal, wherein the timing selection signal is dependent upon a read current of at least one data storage cell of the plurality of data storage cells.