Mutual capacitance sensing using a self-capacitance sensing device

摘要

Apparatuses and methods of mutual-capacitance sensing with a capacitance-sensing circuit, such as a self-capacitance sensing device (CSD). One apparatus includes an input node coupled to a capacitance sense pin to couple to a first electrode of a sense array, a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array, logic circuitry coupled to the TX signal generation circuit and the input node. The logic circuitry is configured to selectively couple a first capacitor to the input node and a second capacitor to the input node timed with the TX signal. The apparatus further includes an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, the digital value representing a mutual capacitance between the first electrode and the second electrode.

主权项

1. A capacitance-sensing circuit comprising:
an input node coupled to a capacitance sense pin coupled to a first electrode of a sense array, wherein the input node is a single signal path of a sensing channel of the capacitive-sensing circuit; a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array; logic circuitry coupled to the TX signal generation circuit, wherein the logic circuitry is configured to selectively couple a first capacitor to the single signal path and a second capacitor to the single signal path timed with the TX signal, wherein the first capacitor and the second capacitor are coupled to ground; and an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, wherein the digital value represents a mutual capacitance between the first electrode and the second electrode, wherein the ADC comprises a comparator comprising a first input coupled to the single signal path and a second input coupled to a voltage reference (Vref), wherein a direct electrical connection is formed on the single signal path between the capacitance sense pin and the first input of the comparator, wherein the logic circuitry is configured to selectively couple the first capacitor and the second capacitor to the single signal path in a non-overlapping manner and timed to capture the RX signal from a first edge of the TX signal and to capture the RX signal from a second edge of the TX signal.