发明名称 |
Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing |
摘要 |
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto. |
申请公布号 |
US8780642(B2) |
申请公布日期 |
2014.07.15 |
申请号 |
US201012872351 |
申请日期 |
2010.08.31 |
申请人 |
Silicon Storage Technology, Inc. |
发明人 |
Widjaja Yuniarto;Cooksey John W.;Chen Changyuan;Gao Feng;Lin Ya-Fen;Lee Dana |
分类号 |
G11C11/34;G11C16/04 |
主分类号 |
G11C11/34 |
代理机构 |
DLA Piper LLP (US) |
代理人 |
DLA Piper LLP (US) |
主权项 |
1. A method of erasing a plurality of flash memory cells in a flash memory structure formed in a semiconductor substrate of a first conductivity type wherein said structure has a first region of a second conductivity type in said substrate; a second region of a second conductivity type in said substrate, spaced apart from said first region, thereby defining a continuous channel region therebetween; a plurality of floating gates, spaced apart from one another, each positioned over a separate portion of the channel region, wherein each floating gate defines a flash memory cell; a plurality of control gates, each associated with and adjacent to one of the floating gates, each control gate having two portions directly and electrically connected to one another: a first portion over a portion of the channel region and not over any of the floating gates, and a second portion over the floating gate associated therewith and capacitively coupled thereto; wherein said method comprising:
applying a positive voltage to each of said control gates to provide capacitive coupling to the floating gates associated therewith; thereby causing tunneling of electrons from each floating gate to the control gate associated therewith. |
地址 |
San Jose CA US |