Decomposition and marking of semiconductor device design layout in double patterning lithography

摘要

Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

主权项

1. A method for decomposing a design layout for a semiconductor device into a plurality of photomasks that may be combined to form an exposure pattern using DPL (double pattern lithography) techniques, said method comprising:
identifying a design layout of an exposure pattern for a semiconductor device, to be decomposed; generating an electronic file of said design layout on a non-transitory computer readable electronic storage medium using a computer at a design level, said electronic file of said design layout including first features each having a first marking designating said first features to be formed on a first photomask, second features each having a second marking designating said second features to be formed on a second photomask, and stitching locations each having a stitching marking designating each said stitching location as a location at which said first and second features meet to form a continuous device feature of said design layout wherein; said semiconductor device comprises an integrated circuit device and said providing said electronic file of said design layout includes marking said design layout according to criteria other than critical dimension, including: marking similarly sized features with the same marking; marking features that substantially determine device speed, with the same marking; providing said non-transitory computer readable electronic storage medium to a mask foundry; and said mask foundry decomposing said design layout based on said electronic file, into a plurality of layouts, and forming a photomask from each said layout.