| 摘要 |
A shift register according to an embodiment of the present invention comprises a plurality of stages, each of which includes a shift register latch unit which sequentially latches input signals and outputs the latched signals to a Q node and a QB node; a pull-up TFT which is turned on by a signal of the Q node in a display mode during one frame period and outputs a gate driving signal of a gate high voltage to a gate line; a first pull-down TFT which, after the gate driving signal of the gate high voltage is output in the display mode, is turned on by a signal of the QB node and maintains a potential of an output terminal at a gate low voltage level; and a second pull-down TFT which is turned on by a touch mode synchronization signal in a touch mode during the one frame period and maintains a potential of the gate line at a gate low voltage level. |
