Calibration of delay chains

摘要

A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

主权项

1. A calibratable delay chain comprising:
a delay chain comprising a plurality of delay stages and adjustment circuitry configured to vary a delay of each of said plurality of delay stages in response to an input value; and calibration circuitry configured to calibrate a delay of said delay chain, wherein said calibration circuitry comprises: calibration control circuitry for controlling said calibration and supplying said input value to said adjustment circuitry; output selection circuitry configured to select an output from a predetermined point along said delay chain; a bypass path for bypassing said delay chain; a digital comparator configured to compare an output from said delay chain and an output from said bypass path; an analogue comparator configured to compare an output from said delay chain and an output from said bypass path; wherein said calibration control circuitry is configured to control said output selection circuitry to output a signal from one point on said delay chain to said digital comparator and to change said input value to said adjustment circuitry in a first direction at a first rate until a change in an output value of said digital comparator value is detected; said calibration control circuitry is configured to respond to said detected change in output value of said digital comparator to control said output selection circuitry to output a signal from a further point on said delay chain to said analogue comparator and to change said input value in a second direction at a second rate starting from a value determined by said input value at which said digital comparator's output value changed value, said second rate being slower than said first rate, a change in value output from said analogue comparator indicating an input value that provides a calibrated delay.