| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock and data recovery circuit, a data reception device and a data transmission and reception system that are tolerant of variations in supply voltage, avoid a false lock state and an unlocked state, and thus have a stable data reception capability.SOLUTION: In order to resolve a difference between a clock phase in a lock condition in a loop including a frequency and phase comparator and a clock phase in a lock condition in a loop including a phase comparator, a first variable delay circuit for applying a first delay time to a data signal and a second variable delay circuit for applying a second delay time to a feedback clock signal are added to the loop including the frequency and phase comparator. |
