| 摘要 |
<p>The present technique relates to a semiconductor memory device having a spare logic, and a manufacturing method thereof. The present invention prevents the size of a cell from being expanded since an additional space is not needed according to a circuit design revision by forming a spare projection diode and a spare resistor in a guide ring region which is located in the outermost part of a transistor. Also, the length of a metal line is minimized by forming the spare projection diode and the spare resistor in a region which is adjacent to the transistor, thereby improving the problem of signal delay.</p> |
