发明名称 Clock signal generator capable of generating stable clock signal, semiconductor memory device having the same, and method thereof
摘要 A clock signal generator can include a clock signal generation unit (18) that is configured to generate a clock signal (CLK). A clock signal control unit (20) is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal (CR) based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.
申请公布号 KR101400695(B1) 申请公布日期 2014.06.27
申请号 KR20070081506 申请日期 2007.08.14
申请人 发明人
分类号 G11C7/22 主分类号 G11C7/22
代理机构 代理人
主权项
地址