主权项 |
1. An integrated circuit comprising:
A. a test data in lead, a test clock lead, a mode select lead, and a test data out lead; B. a linking module having:
i. a test data input connected to the test data in lead, a test clock input connected to the test clock lead, a mode select input connected to the mode select lead, and a test data output connected to the test data out lead;ii. a first test data in output, a first mode select output, and a first test data out input;iii. a second test data in output, a second mode select output, and a second test data out input; andiv. an augmentation instruction shift register having an input coupled to the first test data out input and to the second test data out input and having an output coupled to the test data output. |