发明名称 SINGLE-ENDED SENSE AMPLIFIER CIRCUIT
摘要 A single-ended sense amplifier and a method for reading a memory cell are disclosed. The method includes the following steps. A bit line is charged according to a control signal. Thereafter, whether the dropoff time of the bit line voltage is greater or less than a predetermined time is deteremined. When the dropoff time of the voltage of the bit line is less than the predetermined time period, a first operation is sensed. On the other hand, when the dropoff time of the voltage of the bit line is greater than the predetermined time period, a second operation is sensed. The dropoff time of the voltage of the bit line is determined according to a parasitic capacitance on the bit line. A logic level of a sensing transistor circuit is retained and an output data signal according to the operation sensed is generated.
申请公布号 US2014177350(A1) 申请公布日期 2014.06.26
申请号 US201213726179 申请日期 2012.12.23
申请人 EMEMORY TECHNOLOGY INC. 发明人 Chen Yung-Jui;Po Chen-Hao;Huang Chih-Hao
分类号 G11C7/06;G11C7/12 主分类号 G11C7/06
代理机构 代理人
主权项 1. A single-ended sense amplifier circuit, comprising: a pre-charge circuit coupled to a bit line to charge the bit line according to a control signal; a sensing transistor circuit coupled to the bit line to read a memory cell; and a latch circuit coupled to the sensing transistor circuit to retain a logic level of the sensing transistor circuit and to generate an output data signal acccording to an operation sensed, wherein when a dropoff time of a voltage of the bit line is less than a predetermined time period, a first operation is sensed by the sensing transistor circuit, and when the dropoff time of the voltage of the bit line is greater than the predetermined time period, a second operation is sensed by the sensing transistor circuit, and the dropoff time of the voltage of the bit line is determined according to a parasitic capacitance on the bit line.
地址 Hsinchu TW