Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos

摘要

An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments.

主权项

1. An integrated circuit device, comprising:
a plurality of dynamic array sections each formed within a respective outer peripheral boundary defined by four or more outer peripheral boundary segments, wherein each of the plurality of dynamic array sections includes a respective gate electrode level that forms a portion of an overall gate electrode level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes three or more linear conductive segments formed within its gate electrode level, wherein the three or more linear conductive segments are formed in a parallel manner to extend lengthwise in a first direction, wherein the plurality of dynamic array sections includes a first adjoining pair of dynamic array sections positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction, wherein some of the three or more linear conductive segments within the gate electrode levels of the first adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections, and wherein each of the first adjoining pair of dynamic array sections is defined such that a respective gate electrode level manufacturing assurance halo portion extends in the first direction away from its co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections, wherein each end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the first adjoining pair of dynamic array sections is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of any portion of the co-aligned linear conductive segments.