| 摘要 |
The circuit (1) has a set of logic gates (4), and a control unit (6) utilized for controlling switching of the logic gages at different times of a clock period. The control unit comprises a set of input gates (2), where each input gate receives one of a set of bits as input, and an output of the input gate is connected to respective logic gates. A reactive load is varied randomly based on a control signal (A0), where the load is connected between an output of an inverting gate and an input of the logic gates. |
