CLOCK SYNTHESIS

摘要

One embodiment of a clock synthesis apparatus can include a clock generator that can provide two or more clock waveforms. One clock waveform from the clock generator can be selected to be an output clock in accordance with an error signal determined by a difference between a level of data in a buffer and a predetermined threshold. The output clock can also be a timing reference waveform for data removed from the buffer. In another embodiment, the error signal can be determined periodically. In yet another embodiment, the output clock domain can be different from the input clock domain of the buffer.

主权项

1. A clock synthesis unit comprising:
a clock generator producing:
a nominal clock waveform,a fast clock waveform, wherein the fast clock waveform is configured to be a relatively faster frequency than the nominal clock waveform, anda slow clock waveform, wherein the slow clock waveform is configured to be a relatively slower frequency than the nominal clock waveform; a clock selection circuit configured to provide an output clock waveform from one of the nominal clock, fast clock and slow clock waveforms; and a data buffer configured to accept input data provided in a first clock domain and further configured to provide output data in a second clock domain, wherein the clock selection circuit is configured in accordance with an error difference between an amount of data contained within the data buffer and a predetermined buffer threshold.