Error correcting codes for increased storage capacity in multilevel memory devices

摘要

Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

主权项

1. An apparatus comprising:
a matrix of memory cells; and a calculation system configured to select an error correction code scheme based at least in part on a first number of non-parity information bits that the matrix is capable of storing, a second number of parity cells of the matrix, and a third number of non-parity cells of the matrix.