Methods for generating a user interface for timing budget analysis of integrated circuit designs

摘要

In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

主权项

1. A method of designing an integrated circuit, comprising:
receiving a netlist of a plurality of partitions of an integrated circuit design including a selected signal path for analysis; automatically generating timing budgets for the plurality of partitions of the integrated circuit design, including timing budgets for the selected signal path; computing timing delays along the selected signal path in response to the netlist; generating by a processor, in alignment, a first cumulative bar chart of the timing delays along the selected signal path and a second cumulative bar chart of the timing budgets for the selected signal path; and displaying the first cumulative bar chart and the second cumulative bar chart in alignment within a graphical window on a display device, wherein the displaying enables a visual comparison of the first cumulative bar chart to the second cumulative bar chart.