| 摘要 |
A synchronization aid device (D2) is part of receiving communication equipment (EQ2) of an IP network, having a primary clock signal consisting of primary clock pulses spaced apart by a first period. This device (D2) comprises i) a counter (C2) required to increment its value by one unit on each primary clock pulse and reset its value to zero each time it reaches a value M, ii) detection means (MD2) required to generate a secondary clock pulse each time the value of the counter (C2) is zero, the secondary clock pulses forming a secondary clock signal having a second period equal to M times the first period, and iii) control means (MC2) required, each time the receiving equipment (EQ2) receives a packet containing at least one first bit having a first value, to initialize the counter (C2) with a chosen value. |
