Logic transistor and non-volatile memory cell integration

摘要

A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.