| 摘要 |
<p>A thin film transistor array panel according to an embodiment of the present invention comprises: a substrate; a semiconductor which is placed on the substrate and has a source area, a drain area, and a channel area; a gate insulating layer placed on the semiconductor; a gate electrode which is placed on the gate insulating layer and overlaps with the channel area; a first interlayer insulating layer which is placed on the gate electrode and has contact holes each of which exposes the source area and the drain area; and a source electrode and a drain electrode which are placed on the first interlayer insulating layer and are connected to the source area and the drain area, respectively, through the contact holes, wherein a plane pattern of the source area and the drain area is same as a plane pattern of the contact holes.</p> |
