| 摘要 |
A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided. |
