| 摘要 |
There is provided a reset circuit in which the necessity for adjusting the constant of the pull-up resistor of the reset trigger signal is eliminated to assure a reliable reset operation. The reset circuit has another function to cancel the reset, even when clocks are stopped on power up. During the normal operation, a clock stop detection signal CALMB takes on the level 'H' so that a reset trigger signal CPURSTB is masked by an OR gate circuit 8. If the clocks are stopped during the normal operation, and the clock stop detection signal CALMB is 'L', the reset trigger signal CPURSTB is passed through OR gate circuits 6, 8 and AND gate circuit 10, and output as a reset output signal RSTB. |
